1. Field of the Invention
The invention relates to a level shift driver circuit, and more particularly, a level shift driver circuit capable of reducing gate-induced drain leakage current.
2. Description of the Prior Art
When the level shift driver circuit is used to control high voltage output, the large voltage difference between gate and drain of an output transistor may cause a gate-induced drain leakage current (GIDL) on the output transistor. The current leakage not only causes greater power consumption but also requires greater area for the high voltage supply circuit to provide such high driving current.
To solve the GIDL current, U.S. Pat. No. 7,646,653 discloses a driver circuit 100 to reduce the GIDL current as shown in FIG. 1. The driver circuit 100 comprises a PXID driver circuit 110, a MWL signal generating circuit 120 and an output driver circuit 130. FIG. 2 shows the timing diagram of the driver 100.
When the driver circuit 100 is in a standby mode, the signal PXID outputted by the PXID driver circuit 110 will be an operative voltage VDD and the MWL signal generating circuit 120 will output the signal MWL of a driving voltage VPP, where the driving voltage VPP is higher than the operative voltage VDD. Since the N-type transistor N1A is turned on and the P-type transistor P1A is turned off, the voltage level of the output terminal OUT of the driver circuit 100 will be pulled down to the ground voltage VSS. In other words, with the aid of the PXID circuit 110, the voltage difference between the terminals of the P-type transistor P1A may be reduced, which results in the reduction of GIDL current when the driver circuit 100 is in the standby mode of operation.
However, when the driver circuit 100 is activated, the signal PXID outputted by the PXID driver circuit 110 will be at the driving voltage VPP and the MWL signal generating circuit 120 will output the signal MWL of the ground voltage VSS if the address bit of the driver circuit 100 is selected. Therefore, the voltage level of the output terminal OUT of the driver circuit 100 will be pulled up to the driving voltage VPP by the P-type transistor P1A. However, since the gate of the N-type transistor N1A is at the ground voltage VSS and the drain of the N-type transistor N1A is at the driving voltage VPP, a significant GIDL current may be induced by the great voltage difference on the gate and drain of the N-type transistor N1A.
Namely, the driver circuit 100 taught in U.S. Pat. No. 7,646,653 can only reduce the GIDL current in the standby mode of the driver circuit 100 but cannot reduce the GIDL current in the activated mode of the driver circuit 100. Consequently, how to reduce the GIDL current in both modes has become a critical issue to be solved.